Description

<style>.e_editor{font:14px/24px Arial,'microsoft yahei','Times New Roman','b8bf53';}.e_editor div,e_editor p,e_editor td,e_editor th,e_editor li{font-weight:inherit;font-size:inherit;font-style:inherit;font-family:inherit;}.e_editor ul{margin:-10px 0 20px;}.e_editor li{padding:5px 0;}.e_table{width:96%;border-collapse:collapse;empty-cells:show;}.e_table th,.e_table td{padding:5px;border:2px solid #eee;}.e_img{padding:10px 0;text-align:center;}.e_p{line-height:20px;padding:0 0 20px;text-indent:0em;}</style> <div class="e_editor"> <div class="e_p"> FPGAs are expensive... and hard to use... and too slow... and difficult to program... and hard to debug... and they draw too much power... and require register-transfer-level (RTL) wizards. That’s the conventional developer widsom, at least. But before you run for the exits, sit and relax, because the conventional wisdom is wrong. </div> <div class="e_p"> Yes, FPGA design will likely take you out of your comfort zone if you’ve never handled an FPGA or ASIC design. But even novices can manipulate FPGAs without resorting to a graduate degree. This isn’t to imply that becoming an FPGA guru overnight is possible, though. Still, the learning curve has moved from a black diamond to more of a rolling hill. </div> <div class="e_p"> The primary drivers behind this change are the improvements seen in all types of FPGA development tools. There has been a greater emphasis on support for soft-core processors, since a significant percentage of new designs employs at least one softcore processor. </div> <div class="e_p"> In many of these cases, the designers are programmers or systems engineers. Consequently, FPGA software vendors enhance their products so that they’re better able to support a growing class of developers. </div> <div class="e_p"> Soft-core processors are an expanding part of the target hardware for reference designs and development kits. Altera’s NIOS II Embedded Evaluation Kit, Cyclone III Edition, is one of many kits designed to facilitate software application development on FGPA platforms. The NIOS II is a 32-bit RISC-style core. Kits like this come with predefined FPGA configurations. Therefore, developers can concentrate on application software with minimal FPGA manipulation (though that’s typically the starting point). </div> <div class="e_p"> Incrementally improving a soft-core processor system design with additional peripherals is a relatively easy process. For example, Xilinx’s ISE Design Suite can be used to construct systems based around its MicroBlaze soft-core processor. </div> <div class="e_p"> Altera’s SOPC Builder provides similar functionality. The design tools incorporate the MegaWizard interface to configure and add more intellectual-property (IP) blocks into the system. The interface allows selected blocks to be modified using custom dialog boxes without delving into the IP’s design. It’s also possible to hide the design, essentially presenting a configurable black box to the developer. </div> <div class="e_p"> Adding IP to a modular framework with a soft-core processor is also easier than working with most FPGA designs. That’s because a framework is provided with the soft-core processor to handle common design attributes, such as address and data bus connections as well as interrupts. </div> <div class="e_p"> Creating a design based on a soft-core processor is often a matter of selecting the desired modules and then configuring them using the MegaWizard. The development tools handle linking and layout. Just specify the pins that will be used to connect with the peripherals. </div> <div class="e_p"> Actel, Altera, Lattice Semiconductor, Xilinx, and other FPGA vendors are all including more peripheral IP that works with their collection of soft-core processors. This makes it significantly easier to replace a microcontroller with an FPGA. The range of FPGA costs and performance has been steadily increasing, with low-end FPGA prices at less than 50 cents and clock rates hitting 1.5 GHz. </div> <div class="e_p"> Why take this approach? Among the many reasons, you could, for example, tie the IP to a system. This allows it to be moved to new FPGAs, eliminating or at least reducing the effects of obsolescence. That’s why standard processor core architectures such as the 8051 and its associated peripherals are available. </div> <div class="e_p"> The challenge is replicating vendor-specific peripherals, and that happens to be where FPGAs shine. Still, the level of expertise that’s required to build a peripheral from scratch or even modify an existing design is much higher than that required to create a custom microcontroller by selecting features from a Chinese menu. </div> <div class="e_p"> On the plus side, it’s a one-time-only process. Also, the same process is used to create custom IP. The main difference from a few years ago is that it’s a markedly easier process. </div> <div class="e_p"> SPREADING THE WEALTH </div> <div class="e_p"> FPGA vendors have soft-core processors optimized for their chip architectures. As noted, a number of popular architectures like the 8051 are available across FPGA architectures. In addition, more new softcore processors are designed for FPGAs that match popular architectures. </div> <div class="e_p"> These processors include ARM’s Cortex M1 and Freescale’s Coldfire. The cores come with a complement of peripherals that can be added to a design, permitting the creation of systems that resemble existing microcontroller designs. As with most FPGA IP, an FPGA vendor’s development tools can utilize these cores. Of course, migrating a design from one vendor’s toolset to another is quite a challenge. </div> <div class="e_p"> Designers who need this level of portability might do well to examine alternatives. Some of these options are available from Altium, Mentor Graphics, and National Instruments. In most cases, these tools provide additional advantages. For instance, Altium Designer handles system design and printed-circuit-board (PCB) layout within the same environment. </div> <div class="e_p"> National Instruments’ LabVIEW is a general graphical programming environment that can target a range of platforms, including FPGAs. It also can handle multicore designs. </div> <div class="e_p"> Originally designed for test and measurement applications, LabVIEW first ran on an Apple Macintosh. Its code now can run on a range of targets, including embedded microcontrollers like Analog Devices’ Blackfin and, of course, FPGAs. </div> <div class="e_p"> NI’s Compact RIO combines a host processor with an FPGA that links the host to peripheral device modules. A Lab- VIEW program that runs on a Compact RIO system is mapped to the FPGA and code that runs on the host. Compact RIO’s modular approach works well for prototyping and in the lab. The Single Board RIO is designed to migrate these designs to an embedded environment. The Single Board RIO Training Module provides a mechanism to experiment with the FPGA. </div> <div class="e_p"> LabVIEW can target FPGAs from different vendors, even though Compact RIO uses a Spartan-3 FGPA. Altium’s Innovation Station is an all-FPGA solution that supports FPGAs from multiple vendors and works with Altium Designer. </div> <div class="e_p"> Altium Designer is similar to LabVIEW in the fact that a single design can target different FPGAs. FPGA vendor development tools typically will allow migration across the vendor’s family of FPGAs. </div> <div class="e_p"> There are other advantages to a system that can target multiple vendors because of the technology differences. For example, some FPGAs are faster to program, so one part might be used in the development process while another is used in deployment. </div> <div class="e_p"> FPGA LOCKDOWN </div> <div class="e_p"> Creating an FPGA design from components is the standard mechanism for designing a system, but obstacles can arise with any complex FPGA design, especially one that contains a soft-core processor. Timing issues are generally high on the list, but other problems can arise as well, especially when using the auto-routing and configuration support of the place-and-route compilers that do the low-level work. </div> <div class="e_p"> To reduce the possibility of problems due to a design being rearranged by these tools, lock the IP down to a particular layout or even a particular location on the FGPA. This enables experts to design and debug the IP, typically the soft-core processor, and to provide it in a form that will always wind up in a known location or layout. </div> <div class="e_p"> FPGA vendor tools provide this capability to varying degrees depending on the vendor. A related feature is the ability to prevent modification or examination of the underlying IP to protect the IP. </div> <div class="e_p"> DEPLOYMENT DEVELOPMENTS </div> <div class="e_p"> Deploying FPGAs, especially flashbased FPGAs, is getting easier. Still, FPGA modules are often the best solution. These platforms can be used for development as well as deployment, reducing the expertise needed to integrate an FPGA into a solution. </div> <div class="e_p"> FPGAs have always found homes in board-level products targeted at military and high-performance computing environments. They’re now starting to move into lower-end solutions, offering flexibility and the ability to lower stock-keeping unit (SKU) count. </div> <div class="e_p"> One example is Diamond Systems’ PC/104 GPIO-MM-21 board, which has 96 digital I/O lines. A single 40-MHz, RAM-based, 200-kgate Spartan II FPGA controls the system. </div> <div class="e_p"> In most cases, these boards are programmed once by the board vendor. That’s because the FPGA development tools were difficult to use. Now that the development tools are becoming easier to use, these platforms may open wider to developers. </div> <div class="e_p"> FPGA hardware is making FPGAs a more suitable target. Meanwhile, FPGA development tools simplify system design and matching software development when a softcore processor is part of the solution. </div> </div>