ALLPCB
Coverage-driven verification (CDV) framework
UVM provides a framework for implementing coverage-driven verification (CDV). CDV combines automatic testvector generation, self-checking, and coverage collection to significantly reduce the time required for design verification.
CDV workflow vs directed testing
The CDV workflow differs from traditional directed testing. CDV starts from verification goals, constructs a testbench that generates and applies testvectors to the DUT, and adds coverage monitors to measure verification progress and identify unverified functionality. Checkers are included to detect incorrect DUT behavior.
Simulation and constraints
Simulation is started after the coverage models and the testbench are implemented. Constraints can be applied on top of the testbench infrastructure to reach verification goals more quickly. CDV environments support both directed and constrained-random testing; constrained-random tests should be used to cover the majority of cases before creating time-consuming directed tests for complex scenarios.
Abstraction and reuse
An abstract, implementation-independent testbench improves readability and reusability.
UVM testbench architecture
A UVM testbench is built from reusable verification components (UVCs). UVM supplies the verification flow and testbench infrastructure so users can replace generic components with IP-specific implementations where needed.
