ALLPCB
Overview
Copper interconnects are a relatively recent technology. After extensive research and development, IC products with copper interconnects first appeared in 1999. Copper interconnect technology is used in designs with minimum feature sizes below 0.18 μm and is applicable to smaller technology nodes such as 0.13 μm and below; it has been adopted in logic IC manufacturing.
Cost and Adoption
The dual-damascene process simplifies copper interconnect fabrication by reducing process steps, so copper interconnects can be less costly than traditional tungsten or aluminum-copper alloy interconnects. As a result, copper interconnects have become the mainstream interconnect technology for advanced IC manufacturing.
SOI, Copper and Low-k Dielectrics
Using an SOI substrate together with copper and low-k dielectric interconnects enables designers to build fast, feature-rich ICs with lower power consumption, improved noise immunity, and high reliability. A typical cross-sectional schematic of a CMOS integrated circuit with an SOI substrate, copper and low-k dielectric interconnects illustrates these choices.
Scaling Beyond 45 nm
As device dimensions scale to 45 nm and below (for example 40 nm, 32/28 nm and 22/20 nm), gate oxide thickness reaches its practical limit because further reduction would cause excessive leakage. High-k gate dielectrics have been developed to replace silicon dioxide and silicon oxynitride. To further improve device performance, metal gates have replaced polysilicon gates. Strain engineering is widely used to enhance electron and hole mobility and thus increase device speed. Selective epitaxial growth of SiGe and SiC is used in CMOS manufacturing to obtain desired channel strain.
Process Integration and Reliability
Self-aligned CoWP plating techniques have been developed to coat the copper surface after copper CMP to prevent copper diffusion and reduce electromigration, improving interconnect reliability. Metal hard masks such as TiN are used for etching low-k dielectrics.
Advanced Lithography and Design-for-Manufacturability
193 nm immersion lithography and double-patterning processes are used to pattern tight line spacings. Source mask optimization (SMO) techniques are applied to pattern contact openings and vias. Designers must work closely with lithography engineers and process teams to optimize designs for high yield, a practice known as design for manufacturability.
32/28 nm CMOS Integration
A 32/28 nm CMOS cross section typically includes a high-k metal gate (HKMG) stack, selectively epitaxial grown SiGe for strain, stress memory technology (SMT), copper ultra-low-k interconnects, and lead-free solder bumps.
STI and Well Implantation
The shallow trench isolation (STI) process used for scaled devices may appear similar to older STI flows, but many details differ because of device shrinkage. For example, some scaled devices require STI oxide with engineered stress to help enhance channel strain, whereas earlier devices used stress-neutral STI fill.
Well implantation and pocket/punch adjust implants form dual wells in CMOS. Because devices are shallower at advanced nodes, junction depths for wells are shallower than in earlier processes.
Gate Formation and Source/Drain Engineering
The gate, NMOS source/drain extensions (SDE) and spacer formation are critical steps. PMOS source/drain regions are often formed by selective epitaxial growth of SiGe and doped in situ during the SEG process, so PMOS may not require SDE or source/drain implants. Unlike older flows, the polysilicon gate is used as a placeholder and is subsequently replaced by a high-k dielectric and metal gate. This flow avoids polysilicon implantation, and the gate work function is controlled by different metal gate materials for PMOS and NMOS.
