Ansys Supports Signoff for Intel 16nm Process

Overview

Ansys power integrity and electromagnetic analysis tools provide support for power integrity, signal integrity and reliability signoff for Intel's 16nm process node, targeting applications such as high-performance computing (HPC), 5G and AI.

Key points

• Ansys Redhawk-SC, Ansys Totem and Ansys PathFinder-SC support power integrity, signal integrity and reliability signoff for Intel 16nm process designs.
• Ansys multi-physics platform supports the 16nm process RF capabilities and other advanced features, enabling chip-related predictive accuracy to accelerate design closure and improve performance.
• Ansys multi-physics solutions have been certified by Intel Foundry Services (IFS) to support signoff verification of integrated circuits designed on Intel 16nm process technology. Ansys and IFS validated an integrated electronic design automation (EDA) flow for customer productivity.

Tools and capabilities

Ansys Redhawk-SC and Ansys Totem are used for power integrity signoff in digital and analog designs. Their cloud-enabled data architectures provide large capacity to support full-chip hierarchical or flat analysis. Ansys PathFinder-SC uses the same elastic compute architecture to support verification of ESD protection circuits across the entire chip.

Manufacturing and collaboration

According to Rahul Goyal, vice president and general manager of Intel's product and design ecosystem support, the collaboration between Ansys and Intel Foundry Services extends support for the Intel 16nm process, including RF features, and aims to provide foundry customers with EDA tools that work on existing design platforms and leverage Intel manufacturing capabilities.

John Lee, Ansys vice president and general manager of the electronics, semiconductor and optics business, noted that cooperation with foundry partners focuses on addressing multi-physics challenges and meeting power, performance and reliability requirements. He said the Ansys signoff platform helps customers accelerate design convergence and ensure predictive accuracy.